IIIT Hyderabad Publications |
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Performance Analysis of Dual Vt Asymmetric SRAM -Effect of Process Induced Vt VariationsAuthors: Mamatha Samson Conference: International Conference on Advances in Computing, Control, and Telecommunication Technologies (ACT 2009 2009) Date: 2009-12-28 Report no: IIIT/TR/2009/244 AbstractThis paper examines the read stability, write ability and leakage power of various dual-Vt configurations, of an asymmetric SRAM cell (Pass cell) in an array considering the process-induced intra-die threshold voltage variations using Ncurve metrics. The effects of process induced Vt variations in 22 different dual-Vt cell combinations are evaluated and compared using Monte Carlo simulations. The comparisons are made with the help of power noise margins and leakage power. The variances and percentage variances from the mean of voltage and current margins for all combinations are estimated and compared. The results help in process variation tolerant design of Pass cell. Full paper: pdf Centre for VLSI and Embeded Systems Technology |
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