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A Novel Architecture For A Low Power And Variable Resolution FLASH ADCAuthor: A Mahesh Kumar Date: 2010-06-26 Report no: IIIT/TH/2010/18 Advisor:Srinivas MB AbstractAnalog to Digital Converter (ADC) is a fundamental component in digital signal processing systems. For high-speed applications, a flash ADC is often used. Resolution, speed, and power consumption are the three key parameters for an analog-to-digital converter (ADC), which cannot be changed once an ADC is designed. While one can use only 8-bit precision from a 10-bit ADC. Such an application is non-optimal, resulting in slower speed and extra power consumption due to full 10-bit internal operation. Flash ADCs architectures commonly use high speed conversion that requires many analog comparators, which in turn cause higher complexity and power dissipation. Moreover, the accuracy of dividing resistors requires high value for reference voltage if the converting resolution is high. In this thesis, a novel architecture for flash ADC is proposed. In this architecture comparators of conventional flash ADC are replaced with CMOS inverters whose threshold can be varied dynamically. A novel peak-detector circuit is employed to achieve variable resolution for the ADC as well as to switch the unused parallel inverters to standby mode. The ADC is capable of operating at 4-bit, 6-bit, and 8-bit precision at a supply voltage of 2.5V, it consumes 21.5mW at 8-bit, 9mW at 6-bit and 3.5mW at 4-bit resolution. The sampling frequency ranges from 0.8 to 1.6 GSPS, and the ADC has a DNL<±0.4LSB, INL<±0.36LSB, SNR of 47dB and SNDR of 46.3dB for 8-bit operation. The proposed ‘inverter-based’ flash ADC operating at 8-bit precision and conventional 8-bit comparator-based flash ADC have been designed, compared and verified for post layout simulations in standard 65nm CMOS technology using thick gate process. It is observed that linear reduction in resolution leads to exponential reduction in power. Full thesis: pdf Centre for VLSI and Embeded Systems Technology |
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