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ESD and Overvoltage Protection Issues in Modern IC TechnologyAuthor: Akshaykumar Salimath Date: 2010-08-11 Report no: IIIT/TH/2010/34 Advisor:Satyam Mandavalli AbstractThe technology evolution and complexity of new circuit applications involve emerging reliability problems and even more, sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD) and Overvoltage stress-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications’ performance, ICs still should comply with minimum standards of failure robustness in order to be commercially viable. Although the topic of IC Protection from ESD and Over voltage induced damages has received attention industry-wide, the design of robust protection structures and circuits remains challenging because the failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate protection against IC failures. This dissertation presents comprehensive design methodology for implementing on-chip ESD protection for LNA and a circuit design technique to overcome Reliability issues in Mixed Voltage IOs. Firstly the various failure mechanisms in Integrated circuits is revised. In the next chapter, the ESD topic in the semiconductor industry is described, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approach is illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem associated with capacitive loading of ESD protection device in LNAs is addressed next. A better methodology for implementing greater level of ESD protection by making use of ON chip inductors is proposed. The passives used in the design of RF Receiver blocks also influence the ESD robustness of LNA. Inductors and capacitors in RF circuits can be implemented either ON chip or OFF chip. In earlier technologies where the passives used to be OFF chip the ESD immunity of the LNA was totally determined by the robustness of ESD protection device. However in modern RF ICs the focus is on full integration to reduce system cost and area. So the passives appear ON chip. In RF ESD Protection it is common practice where capacitors and inductors in the circuit used for matching and frequency selection, are used to tune out ESD frequencies. In a Cascode LNA with inductive degeneration where ON chip inductors are used they can be used for ESD protection. Two cases are considered. In the first case a common design practice where the ESD device is positioned at the gate of LNA is considered as shown in Figure 1.1 and it is shown that the level of ESD protection is very much limited as the frequency of operation increases. In the second case we shift the ESD device away from the gate of LNA and make use of ON chip inductors to enhance the level of ESD protection. This method also has been shown to that the advantage that the capacitive effects are reduced as we move away from the gate of LNA. Consider the topology in Figure 1.1 (a).As the frequency increases the capacitive reactance decreases and the ESD device begin to shunt more signal power to the ground. With this topology around 5GHz frequency of operation the achievable level of ESD protection may be reduced to 500V HBM which leads to early failure of the circuit.The proposed methodology for providing ESD protection for LNA using ON chip inductors is shown in Figure1.1 (b).By shifting the ESD protection device away from the gate of LNA and towards antenna the capacitive effects are reduced which means that the degradation of power gain and noise figure is less for given ESD device size. Also the required matching of 50Ω for maximum power transfer can achieved by varying both gate inductor Lg and source inductor Ls providing higher degree of freedom. Also the presence of gate inductor suppress steep current transients. With the proposed methodology upto 4KV HBM ESD protection is shown to be possible without much degrading the LNA performance parameters where as with the existing approach maximum protection of 2KV HBM was possible at 2.1GHz. The analysis is validated by simulation for 2.1GHz LNA with ON chip Spiral inductors and ESD protection in Cadence Design Suite using IBM CSOI7TF 180nm RF Technology. The Overvoltage protection issues in Mixed Voltage IOs is addressed next. When two digital logic devices having different power supply levels are coupled an interface is generally required to prevent damage to transistors in the device having the lower power supply level. In the mixed-voltage I/O buffers, that interface the high-VDD signal environment of the old I/O specifications to low-VDD environment for low power consumption of core circuits, the voltages across transistor terminals should be managed carefully to overcome reliability problems, such as gate-oxide overstress, hot-carrier degradation, and the undesired circuit leakage paths (for the conduction of the parasitic drain-to-well pn-junction diode in the main pullup PMOS device). For example in 3.3V PCI-X bus connected to a transceiver with core circuits operating at 1V and peripheral buffers operating at 2.5V these transistors are to be protected from a voltage of 3.3V that may appear on the bus during its operation. A 2.5V device can safely drive its own IO pin during transmit mode. However when IO pin of 2.5V device is being driven by neighboring 3.3V device, the 2.5V device must include protection circuits attached to the IO pin. Various approaches to protect IO Buffer against Overvoltage induced damages in mixed voltage environment have been proposed. These various approaches have several disadvantages in terms of fabrication cost, reliability issues, area considerations etc. When 3.3V appear on the PAD gate tracking and bulk tracking circuits proposed in this work shift the gate voltage and bulk voltage of PMOS to the PAD voltage namely 3.3V.This reduce the gate oxide stress and standby current in PMOS. Further this circuit reduce substrate leakage currents to negligible values. In addition the protection of NMOS against gate oxide overstress is taken care of by transistor stacking. The proposed circuit is validated by HSpice simulation in 130nm CMOS process and the performance is compared with existing circuits. Full thesis: pdf Centre for VLSI and Embeded Systems Technology |
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