IIIT Hyderabad Publications |
|||||||||
|
Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-Grouped Sliding-Window TechniqueAuthors: Rahul Shrestha,Roy Paily Conference: IEEE 5th International Symposium on Electronics System Design (ISED-2014 2014) Date: 2014-12-15 Report no: IIIT/TR/2014/68 AbstractThis paper proposes a un-grouped-sliding-window-technique (UGSWT) and a state metric normalization technique for logarithmic maximum-a-posteriori-probability (LMAPP) algorithm. We have suggested a decoder architecture based on these techniques for high throughput application. Application-specific-integrated-circuit (ASIC) implementation of the proposed decoder is carried out in 90 nm complementary-metal-oxide-semiconductor (CMOS) process and it has achieved a throughput of 612 Mbps at a maximum clock frequency of 625 MHz with an energy efficiency of 0.1 nJ/bit. Functional verification of the implemented channel decoder is carried out using field-programmable gate-array (FPGA) which is interconnected with logic analyzer via high-speed-data-transfer card. Bit-error-rate (BER) performance of the implemented decoder has shown a coding loss of approximately 0.2 dB in comparison with the simulated BER values. Full paper: pdf Centre for VLSI and Embeded Systems Technology |
||||||||
Copyright © 2009 - IIIT Hyderabad. All Rights Reserved. |