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PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit DesignAuthors: Prateek Gupta,Shirisha Gourishetty,Harshini Mandadapu,Zia Abbas Conference: IEEE International Symposium on Circuits and Systems (ISCAS 2019 2019) Date: 2019-05-26 Report no: IIIT/TR/2019/63 AbstractEnormous increase in process variations (due to progressive CMOS technology scaling) along-with the temper- ature and supply voltage variations are severely degrading the fabrication outcome of digital circuits i.e. circuits are not accom- plishing the specification bounds of the required performances. Therefore, process and operating variations aware optimization has become a very essential task in VLSI design. Moreover, many specifications in a circuit have challenging trade-offs, hence demand effective optimization skills. With this vision, this paper presents optimization algorithm based robust transistor sizing for various nanoscale CMOS digital circuits. The objective is to minimize the static i.e. leakage power without degrading the operating frequency (i.e. keeping the propagation delays in bound) and area. The reported results are shown for 32nm CMOS Metal gate High-k model parameters, however methodology is equally valid for further scaled technology nodes. The Overall reduction in leakage power obtained is up to 88% keeping bound on the critical path delay. The temperature range and supply voltage has been taken between −55 ◦ C to +125 ◦ C (for automotive applications) and 0.90V to 1.10V (±10% variations) respectively at 3-sigma design. Full paper: pdf Centre for VLSI and Embeded Systems Technology |
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