IIIT Hyderabad Publications
Low Power Charge Mode CMOS Implementation of Multichannel Signal Sensing Systems
Author: Bhuvanan Kaliannan
Report no: IIIT/TH/2016/50
Advisor:Vijaya Sankara Rao P
In the recent years there has been a continuous demand for increase in the power performance of the wireless electronic systems. This has been due to the tremendous increase in the data rate of the signal acquisition systems, thus resulting in huge power consumption at the RF transceiver and the A/D converter. Various data compression techniques have been used for quite some time to reduce power consumption. The recent theory of compressed sensing (CS) enables more efficient acquisition of signals at a rate much lower than the Nyquist rate. Further extension in the theory of CS has resulted in distributed compressed sensing (DCS), through which multiple signals can be acquired and reconstructed simultaneously. This brings about an increased compression efficiency, or in other words, the signal ensemble can be reconstructed with a fewer number of measurements when compared to a single channel CS. So, the need for low power signal compression circuits along with an efficient architecture for multichannel signal acquisition are the issues addressed here. In this work, a few low power hardware realizations of these data compression systems in analog domain before analog to digital conversion have been realized. Initially, a capacitor charge redistribution based multiply and accumulate (MAC) circuit capable of operating at very low power is introduced to perform evaluation of a linear equation. The application of this technique is the core contribution to the circuit level aspect of this work. Firstly, this circuit has been successfully utilized to realize a 2-D discrete cosine transform (DCT) completely on hardware in analog domain. The complete 8-point DCT architecture has been implemented in a 1.8 V, 0.18 μm digital CMOS technology. The performance of the implementation shows an average power consumption of 2.16 mW, a PSNR of 23.4 dB and the system occupies an active area of 0.0667 mm 2 . A completely digital implementation of the same system has been performed to compare the power consumption. It is observed that the proposed system utilizes only 1/5 th of the power of digital implementation. Secondly, a wireless capsule endoscopic system has been built on an embedded platform to evaluate the complexity of data compression of a multicamera scenario. Following that, an application specific integrated circuit (ASIC) implementation of a low power multichannel signal acquisition system based on the principle of distributed compressed sensing (DCS), thereby saving power and hardware complexity has been performed. The sensing operation has been realized in the charge domain using the mentioned switched capacitor technique based vector matrix multiplication (VMM) and thus consuming very low power. The technique has been tried upon two different signal ensembles, a) images sensed using CMOS imagers and b) real time neural or EEG signals. The respective systems have been implemented in a 1.8 V, 0.18 μm CMOS technology and is capable of sensing upto 64 EEG signal channels and 16 images simultaneously. The system performance has been tested with a set of EEG signals from practical neural recordings and the results show an average PSNR of 29.17 dB while sensing 64 channels at a compression ratio of 1/4, whereas the performance measures of the DCS imager system show a compression ratio of 1/4 with a power consumption of 36.8 mW per channel while sensing 16 channels simultaneously. The compressed analog signals in all of the above mentioned systems are digitized with an 8 bit ADC. The binary weighted capacitor (BWC) array based 8 bit SAR ADC has also been designed in the same technology targeting the specifications of these systems. The ADC is measured to operate with 7.97 effective number of bits (ENOB) and SINAD of 49 dB while consuming a power of 2.486 mW including the band gap reference (BGR) and associated buffer amplifiers. Finally, an ASIC consisting of a single channel CS based EEG acquisition system has been designed and fabricated which is capable of compressing sampled points in batches of 64 each while occupying an active silicon area of 1.25 x 0.85 mm 2 . In summary, a low power circuit to perform VMM in analog domain has been proposed and a few compression systems and architectures based on compressed sensing have been designed and implemented followed by a system on chip (SoC) realization.
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