IIIT Hyderabad Publications
MIL-STD-1553+: AN ENHANCED INTEGRATED CONTROLLER AND TRANSCEIVER UPGRADE FOR MIL-STD-1553B AT 100-Mb/s
Author: Prateek Pendyala
Report no: IIIT/TH/2016/66
Advisor:Vijaya Sankara Rao P
Over the past three decades, there has been a continuous demand for an increase in the transmission data rate in the aeronautical electronics and communication technologies. This has resulted in the update or creation of new defense and aerospace standards. MIL-STD-1553B is one such bus standard, extensively used in the aerospace and aircraft industry which currently falls short of the modern-day payload requirements as its links support a bandwidth capacity of 1-Mb/s. Present day solutions resort to using an aggregated use of numerous serial buses along with multiple MIL-STD-1553B buses to accommodate high bandwidth inter-aircraft communication requirement. This often leads to less deterministic and complicated systems which require a high cost to develop, integrate, maintain and test. This thesis focuses on improving the bandwidth performance of legacy MIL-STD-1553 data bus by retrofitting redesigned 1553 controllers and analog transceiver upgrades to drive the existing buses at higher data-rates. Therefore, this work explores the enhancement at both digital and analog levels in order to minimize wiring complexity, cable weight and integration cost/time while retaining the valuable features of legacy 1553 standard. Firstly, this research proposes a hardware realization of a 100-Mb/s enhanced data rate MIL-STD-1553B digital controller chip: MIL-STD-1553+, for this purpose. This controller features an integrated remote terminal, bus monitor and bus controller, thus offering a complete 1553 solution at this increased throughput. This work first carried out a comparative study of the reported power and critical path timing aspects of possible architectural techniques with which the existing 1-Mb/s controller design can be improved. Based on this study, a finalization of a synchronous back-end and host processor interface to a true dual port memory to facilitate faster read-and-write memory accesses during controller run-time. A suitable technique of employing high speed majority-based free-running decoders has been chosen at the protocol controller unit‟s front-end interface to receive 100-Mb/s 1553 data. These dual-redundant decoders incorporate both inverted and non-inverted clocks in order to bring the overall clocking rate down to 800-MHz, which conventionally would need a clock of at least 1.6-GHz, thus reducing the power dissipation of the suggested controller. This thesis also suggested partitioning the existing protocol control architecture into two concurrently running state machines which enable the scaled-up scheduling, storage and retrieval of 1553 messages, at 100-Mb/s bit-rate over channel. Finally, the throughput and area-power performance analysis done for a gate-level synthesis and post-layout simulation on a 65-nm, 1.2 V CMOS technology node respectively. This enhanced integrated controller is also implemented on FPGA and checked for block and system level functionality using software logic analyzer IP‟s. Secondly, low power hardware realization of a legacy 1553 analog transceiver upgrade in a 1.8 V, 0:18 m CMOS technology has been made to be able to receive upto 100-Mb/s. Moreover, this transceiver upgrade will support existing legacy 1553 hardware and devices not dedicated to this boosted data rate as well. For this design, we propose a power-saving technique which equalizes the channel inter-symbol interference (ISI) at 100-Mb/s, based on a reconstructed discretized eye diagram accumu-lated after averaging out a large set of comparator decisions, clocked at only 1-MHz. This work presents the working principle, analog design components and digital histogram processing algorithm associated to this transceiver upgrade in detail. This thesis post-layout simulated each design component in this upgrade to verify functionality and followed this with a throughput performance analysis of this system in a communication environment, to observe an optimum error-rate performance.
Full thesis: pdf
Centre for VLSI and Embeded Systems Technology
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