IIIT Hyderabad Publications
Design and Analysis of CMOS Analog Front-End Circuits for High Speed Full-Duplex and Avionics Data Communication
Author: Divya Duvvuri
Report no: IIIT/TH/2016/71
Advisor:Vijaya Sankara Rao P
With the scaling of CMOS feature size into sub-100 nm technology nodes, data rates in the order of giga hertz per second are possible. Input / Output (I/O) interfaces and communication media are the mains bottlenecks to achieve high data rates of the communication systems. The main limitation of the communication media is its limited bandwidth, due to which a high frequency signal passing through it experiences intersymbol interference (ISI) thereby distorting the transmitted data. The limitations imposed by the communication media are overcome by the use of additional circuitry and better communication schemes in the interface devices. Additional circuitry such as equalizers are used in the transceivers to nullify the ISI and distortions due to the communication media. Also, better signaling schemes are also employed in the interfaces to reduce the effects of communication media on the data transmitted through it. Therefore, these techniques allow us to achieve high data rates with the existing communication media. In this work, circuits to nullify the ISI and distortions of the communication media (low loss and high loss) and the use a different signaling scheme to increase the throughput through communication media are discussed. Initially, an analog front-end transceiver for enhanced data rate MIL-STD-1553B, called E-MIL-STD-1553 suitable for avionics and military applications is proposed. This work proposes an analog front-end transceiver supporting 100-Mbps data rate in a multi-drop bus environment, over a cable length of 100 meters for a target bit error rate (BER) of 10 −12 , while retaining all other specifications of MIL-STD-1553B. Complete E-MIL-STD-1553 transceiver is designed and implemented in a 3.3 V, 65 nm CMOS technology. E-MIL-STD-1553 analog transceiver is implemented in Verilog-A and Verilog-HDL respectively. Performance results shows a power consumption of 12.85 mW at 100-Mbps data rate for a 100 percent transmitter duty cycle, occupying an area of 199017 μm 2 , for a target BER of 10 −12 . Secondly, a new current mode continuous time linear equalizer (CTLE) with charge mode pole-zero adaptation scheme is proposed. The proposed equalizer is realized with common gate (CG) topology using switched capacitor based pole-zero adaptation to suit varying channel characteristics. The input impedance of the CG-CTLE is made equal to the characteristic impedance of the off-chip link, hence eliminating the need for a separate resistive termination. Since the proposed CG-CTLE acts as the first stage of the current mode receiver, there is no need for a separate trans-impedance amplifier or a pre-amplifier. The proposed CG-CTLE is implemented in a 1.1 V, 65 nm CMOS technology. The performance results show that it achieves a data rate of 15-Gbps while equalizing the loss of a 7.5 inch FR4 PCB trace. It also offers an input impedance of 44.6 ohm, SNR of 23 dB and a bandwidth of 7.575 GHz and consumes a power of 13.9 mW. Lastly, a new hybrid circuit topology for simultaneous bidirectional signaling across global short (3-mm) and long (10-mm) on-chip interconnects in a multi-channel signaling environment is proposed. The proposed hybrid circuit transmits the outbound signal and simultaneously receives the inbound signal from the combined signal, which is a superposition of the outbound and inbound signals. This work is implemented in 1.1 V, 65-nm CMOS technology. Post-layout results show that the proposed hybrid circuit operates at a data rate of 16-Gbps/ch over a 3-mm and 10-mm on-chip interconnects in a eight parallel channel environment and it achieves a transmitted signal swing of 520 mV and a received signal swing of 108 mV for a power consumption of 35.65 mW. In summary, interface circuits such as equalizers are proposed to nullify the adverse effects of high loss communications channels and hybrid circuit is proposed to increase the overall throughput of the system.
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