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Hardware-Efficient and Reconfigurable VLSI Architectures & Techniques for Spectrum Sensing in Cognitive RadioWireless NetworksAuthor: Mahesh Murty Date: 2018-05-01 Report no: IIIT/TH/2018/19 Advisor:Rahul Shrestha AbstractWireless communication has expanded its horizon in almost every aspect of human lives and its consequence is rapid surge in the demand of spectral resource. Electromagnetic spectrum is a gift of nature and such spectrum bands cannot be increased beyond certain limit. Presently, spectrum is licensed by government agencies to the interested parties by accepting a license fee. At the time of allocation, it is assumed that the licensed party will be utilizing the spectrum up-to its full potential i.e. 100% of the time. Hence the frequency bands to be utilized by the primary user are decided a-priori irrespective of its dynamic utilization status. On the other side with the advent of technologies like IoT, wearable consumer electronics and smartphones etc. applications are becoming bandwidth hungry and the number of connected devices are increasing drastically. Gardner technology research, a premier IoT research company claims that in the year 2015, 4.9 billion devices were connected to the internet and by 2020 this figure will reach to 20.8 billion. Hence with such an exponential increase in the number of connected devices, we will soon be facing scarcity of the electromagnetic spectrum in near future. Cognitive Radio is an innovative technology with unprecedented level of intelligence and capability to enhance the system capacity as well as spectrum agility of wireless communication systems. It mitigates the problem of spectrum scarcity with the aid of opportunistic access of spectrum. This work is dedicated towards developing hardware efficient and reconfigurable spectrum sensing architectures as well as techniques from VLSI design and implementation perspectives. We propose enhancements to the widely used energy detector design which helps in reducing the overall hardware resources (like adders and multipliers) consumed by 46% and alleviates the memory footprint by more than 95%. Further the conventional energy detector design is extended for wide band sensing applications without compromising on detector performance. We also present reconfigurable VLSI architectures for cyclostationary spectrum sensor which aids in sensing OFDM signals constructed with a variety of sub-carrier lengths. We suggested a novel selective sampling based reconfigurable cyclostationaryspectrum sensor which reduces the memory requirement by 99% and other resources by 33%. To evaluate the performance of these architectures, extensive computer simulations are carried out and detector architectures are implemented on an FPGA platform to verify the timing and functionality. Such verification has been carried out by feeding real-world RF signals captured from standard-RF SDR front-ends. Finally, ASIC syntheses and post-layout simulations of these architectures in 90 and 65 nm-CMOS technologies are carried out and its implementation results are compared with the stateof-the-art. Full thesis: pdf Centre for VLSI and Embeded Systems Technology |
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