IIIT Hyderabad Publications |
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Core Compact Models for Symmetric Multi-Gate Ferroelectric Field effect TransistorsAuthor: haranadha.rm Date: 2018-07-28 Report no: IIIT/TH/2018/43 Advisor:Srivatsava Jandhyala AbstractThe integration density achievable in Complementary Metal-Oxide-Semiconductor (CMOS) technology is limited by the leakage power seen in nanoscale transistors. Efforts to overcome the bottlenecks of power dissipation set by classical Boltzmann physics, resulted in exploration of new transistor architectures having novel transport mechanisms in channel. Ferroelectric FETs use the negative capacitance phenomenon to achieve low subthreshold slopes and have good potential to replace the classical Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The transport mechanism of the channel remains unmodified and these novel transistors are fabricated by depositing a ferroelectric material on top of the gate oxide of a conventional transistors. The subthreshold slope (SS) in a ferroelectric device can go below the Boltzmann limit of 60 mV/dec, resulting in low leakage power in FeFET devices. Further, the current boosting observed in these transistors around the threshold region, aids in improving the speed of operation of these devices. In this thesis, we present hysteresis free operation conditions for Ferroelectric FETs, and derive the core compact models of Symmetric Double-Gate Ferroelectric Field Effect Transistors (SDG-FeFET) and Pillar Gate ferroelectric Field Effect Transistors (Pillar-FeFET). The quasi-static terminal-charge models proposed are shown to match very well with exact numerical terminal charge integrals, for all bias conditions and across various device parmeters. The proposed models are integrated into a professional SPICE simulators using the Verilog-A interface. Different combinational, sequential and SRAM circuits are built using SDG-FeFET and Pillar-FeFET transistors and improvement in their switching behavior is demonstrated through SPICE simulations. Full thesis: pdf Centre for VLSI and Embeded Systems Technology |
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