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FPGA Based High Performance Asynchronous Arithmetic Logic Unit and Asynchronous Finite State Machine Controller using Modified 4-Phase Handshaking ProtocolAuthor: Nikhil Bhandari Date: 2018-12-14 Report no: IIIT/TH/2018/85 Advisor:Shubhajit Roy Chowdhury AbstractThe rapid advancements in the field of semiconductor technologies has paved the way for high speed embedded systems that require high speed of operation, lower power dissipation and robust to electromagnetic noises and interference. The synchronous digital system have been a successful alternative due to simplicity of design but the advancements in the embedded system has imposed major challenges in the simultaneous reduction of delay and power consumption. The reduction in clock period in synchronous design enables higher operating frequency that enhances the clock synchronization complexity and dynamic power consumption leading to the surge in the demand of asynchronous architecture. The clock routing and power consumption issue in synchronous design have been eradicated with the concept of (globally asynchronous locally synchronous) GALS architecture in the year 1975’s. There was no global clock in the design and the sub-modules in the design interact with each other using asynchronous handshaking protocols. The highest operating frequency in GALS architecture was still constrained and limited with respect to the slowest sub-module clock frequency. The fully asynchronous architecture eradicates this limitation since the data transfer is irrespective of clock transitions and depends upon the availability of valid data in order to transfer from source to receiver end. In this thesis, we have proposed the design of modified 4-phase handshaking protocol on the lines of existing standard 4-phase protocol developed earlier for data communication in asynchronous circuits. The proposed protocol has achieved better performance in terms of speed by taking 1-cycle lesser than the existing 4-cycle implementation of standard 4-phase with minimal area overhead. The simulation results obtained for the design of asynchronous ALU based on modified 4-phase handshaking protocol performs better than the existing synchronous and asynchronous standard 4-phase design by executing higher number of instructions in a given time. The time taken in simulation experiment was computed by taking fixed data set of random instructions including ADD, SUB, OR, XOR etc that showed 1.4x increase in the performance in comparison with the asynchronous ALU implemented using standard 4-phase protocol design. The simulation result for the design of asynchronous FSM based on modified 4-phase handshaking protocol outperforms the number of bit sequences detected in a non-overlapping fashion(speed) by existing synchronous and asynchronous standard 4-phase design. The results indicate an increase in speed of 1.65x as compared to the synchronous design and 1.4x in comparison with the design based on asynchronous standard 4-phase protocol. Full thesis: pdf Centre for VLSI and Embeded Systems Technology |
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