Optimizing Compilers for High Performance Architectures

Having hit the Power Wall and Memory Wall instead of going for increasing clock speeds industry is moving towards packing multiple cores either homogeneous or heterogeneous onto a single chip. However now the burden is put on the application programmer, and system software like compilers, run-time systems to translate this raw computing power into application performance gains. Along with multi-cores there are other competing architectures like GPGPUs. To reap performance benefits from these varied architectures many problems need to be addressed at the level programming language abstractions and also in compilers and run-time systems.

We have been looking at applying machine learning techniques in the context of compilers and run-time systems, auto-tuners and techniques for exploiting parallelism in irregular applications.

Faculty

1. R Govindarajulu (Head)