IIIT Hyderabad Publications |
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A Memetic Algorithm based PVT Variation-aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell DesignAuthors: Zia Abbas,Salman Ahmed Journal: IEEE Date: 2019-11-06 Report no: IIIT/TR/2019/125 Full article: pdf Centre for VLSI and Embeded Systems Technology |
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