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Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization AlgorithmsAuthors: Prateek Gupta,Harshini Mandadapu,Shirisha Gourishetty,Zia Abbas Conference: International Symposium on Quality Electronic Design (ISQED-2019 2019) Location Santa Clara, CA USA Date: 2019-03-06 Report no: IIIT/TR/2019/81 AbstractIn this paper, the optimal transistor sizing of the digital cells has been obtained using Simulated Annealing algorithm and an Artificial Bee Colony algorithm and their results have been compared with nominal results for various nanoscale CMOS digital circuits. The goal is to minimize the leakage power keeping the other performance parameters such as propagation delays and the area in the bound. The simulations are done using HSPICE tool for 45nm and below using Metal gate High k Predictive Technology Model cards. To make sure of the unaffected working of all cells in the automotive applications, the temperature range and supply voltage has been taken between −55 o C to 125 o C and 0.95V to 1.05V respectively. The Overall reduction in leakage power achieved in the logic cells is up to 70% without any penalty in the critical path delay. Full paper: pdf Centre for VLSI and Embeded Systems Technology |
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