IIIT Hyderabad Publications |
|||||||||
|
A Memetic Algorithm Based PVT Variation-Aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell DesignAuthors: Zia Abbas,Salman Ahmed Date: 2019-11-17 Report no: IIIT/TR/2019/158 Full paper: pdf Centre for VLSI and Embeded Systems Technology |
||||||||
Copyright © 2009 - IIIT Hyderabad. All Rights Reserved. |