IIIT Hyderabad Publications |
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Implementation of TRNG with SHA-3 for Hardware SecurityAuthor: K. ANNAPURNA 2018900077 Date: 2022-07-06 Report no: IIIT/TH/2022/107 Advisor:Zia Abbas AbstractRandom Number Generators (RNGs) are the solution for cryptographic applications to enhance hardware security. These RNGs should have three specific properties unpredictability, aperiodic, and good statistical criteria. This brief presents a True Random Number Generator (TRNG) based on Ring oscillators' jitter with MLFSR. The MLFSR is augmented with a set of prime primitive polynomials, Boolean, and nonlinear functions to attain a non-linear, unpredictable, and extended sequence period. Paper mainly focused on achieving high randomness by integrating the TRNG with a new promising crypto engine Keccak as a post-processing block, leading to more extensive security in data transfer, encryption keys, data authenticity of ICs, and IoT based applications. The TRNG design is coded in Verilog HDL and implemented on the FPGA Zed board. Hashing is performed with a throughput of 2.4Gbps at 100MHz either with RNG data or SHA data. The HRNG (Hardware Random Number Generator) is an integrated block of TRNG and hashing along with the IP cores of memory, clock Generator, and Integrated Logic Analyzer, implemented on the FPGA hardware. Evaluated the randomness of the generated non-deterministic bit streams (10Mb) using the NIST 800-22 & Diehard test suite and successfully passed. Full thesis: pdf Centre for VLSI and Embeded Systems Technology |
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