Algorithm Driven Transistor sizing based Power-Timing Optimization Methodology for CMOS Digital Circuits

Abstract

During the past few decades, the semiconductor VLSI industry has distinguished itself both by the rapid pace of performance improvements, and by a steady path of constantly shrinking device geometries. MOSFETs upon downsizing, have met the world’s growing needs for electronic devices like computing, communication, entertainment, automotive, and other applications with steady improvements in cost, speed, and area. But the device density has led to increased power consumption. Hence, Leakage, along with propagation Delay are the key metrics to evaluate the performance of any digital circuit. In nano-scale technologies(<45nm), static power occupies a significant share in the total power budget thereby prioritizing the need for leakage reduction techniques. Performance optimization of CMOS based circuits gains more significance for nano scale technology nodes. Variations in operating parameters such as supply voltage, temperature etc. have profound effects on power-delays specifications. The non-homogeneity in process parameters at such scaled technologies hampers the yield of the final designs. Performance degradation over time is another important factor determining the lifetime and reliability of an IC. In this work we develop a framework of algorithms to optimize digital circuits for low power and high performance applications. A wide range of analysis such as sensitivity of the circuit, correlation between parameters etc has been performed to understand the functioning in response to transistor sizing of digital cells. The first stage of this work aims to optimize basic digital cells through transistor sizing using the proposed optimization algorithms like Pareto Harris Hawk optimization algorithm, Glowworm Swarm optimization algorithm, Strength Pareto evolutionary algorithm-II and Neighbourhood Cultivation Genetic algorithm. The resultant system design becomes robust to withstand fluctuations caused by process, aging and operating parameters apart from providing highly improved leakage-delay performances. The second stage of this work involves optimization complex circuits. We have proposed a framework to optimize the complex circuits by selectively replacing the basic cells with the optimized sizing. The proposed framework deconstructs a given circuit into its constituent basic cells. It does a wide range of analysis such as sensitivity, the correlation between process parameters, load analysis, screening of insignificant parameters, and mismatch analysis to generate robust sizing. The algorithms generate sizing that can be used at multiple instances across different circuits. Thus the total number of design variables remains within a limit even when the cell count increases across circuits. The proposed framework then reconstructs the circuit with these optimized cells to improve the power-delay front. While replacing the nominal with the optimized sizing for each cell, the tool identifies the load it has to drive, the path (critical/ non-critical) it is present in and its driver modules in the path. The basic cells are selectively replaced with the optimized sizing using the proposed techniques: Backward traversal replacement technique and Partitioning large basic cells. Results have shown a substantial reduction in leakage power and propagation delays in addition to minimizing human effort