Innovative Solutions for LDO Design Challenges in the Era of Expanding 3D NAND Flash Arrays: A Multi-Loop FVF Driver Topology Approach

Abstract

In the current digital era, there has been an exponential surge in the demand for data storage and retrieval. This escalating need is propelled by a diverse range of applications, spanning from cloud computing and data centers to mobile devices and embedded systems. NAND flash memory, a non-volatile storage technology, plays a pivotal role in meeting these demands and is extensively employed in solid-state drives (SSDs), memory cards, and various other applications. Its notable feature is its high storage density, enabling the storage of substantial volumes of data in a compact and efficient form factor. Industries have recently favored 3D NAND Flash over Traditional NAND Flash, where the ”3D” denotes the vertical stacking of memory cells in multiple layers, akin to a skyscraper, to amplify storage density. While this stacking brings benefits, it presents challenges for analog circuit design engineers. As the number of layers increases, so does the load capacitance, introducing complexities in design as each new generation witnesses a rise in Load Capacitance. This challenge persists despite the growing number of vertical layers, particularly affecting the development of a robust and stable Low Dropout Regulator (LDO) amidst the increasing load capacitance in each generation. Moreover, the escalating layer count necessitates a proportionate increase in the number of LDOs to adeptly supply power to this expansive distributed network. To tackle the aforementioned challenges, the thesis introduces a novel LDO featuring a Flipped Voltage Follower based driver (FVF), deviating from conventional drivers. This innovative design offers increased robustness, especially when applied to a 3D NAND Flash memory array, surpassing the capabilities of traditional architectures. The thesis advocates for a dualloop scheme to enhance the transient performance metrics of the LDO. This proposed scheme not only diminishes settling time but also reduce the overshoot/undershoot voltage in comparison to existing state-of-the-art designs. Moreover, the thesis demonstrates how this structural approach can be extended to efficiently handle extensive distributed loads.