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Digital VLSI Architectures of Multiple-Radix Maximum-A-Posteriori and Turbo Decoders for Low-Power Wireless Communication ApplicationsAuthor: Ashutosh SHARMA Date: 2019-05-18 Report no: IIIT/TH/2019/51 Advisor:Rahul Shrestha,Prasad Krishnan AbstractTurbo codes perform excellently with regard to error correction in physical layer of wireless communication networks. Near Shannon limit bit-error-rate performance of turbo decoders is the key factor that makes it an important aspect of channel decoding. With the surge of expanding wireless communication and very large scale integration (VLSI) industries around the world , it is essential to design a VLSI architecture of flexible data rate channel decoder for targeting the physical layer of next generation 5G standards. With the Moore’s law approaching towards the steady state, it is high-time for the researchers to work on new architectures to enhance the performance for any application, rather relying on CMOS technology scaling. Hence, this motivates us to carry out this work on VLSI architectures for channel decoders. We propose flexible-architecture for soft-input soft-output (SISO) decoder with radix-2/4/8 modes to support multiple data-rates. This work presents designs of major internal blocks of SISO decoder using extensive steering logic to support multiple radix operating-modes. These architectures enable efficient clock-gating of our decoder for low-power consumption in different operating modes. Subsequently, we have aggregated eight SISO decoders with quadratic-permutation polynomial (QPP) interleavers/de- interleavers to design parallel turbo decoder architecture which can operate in multi-radix mode. Suggested SISO decoder is application-specific integrated-circuit (ASIC) synthesized and post layout simulated in UMC 65 nm-CMOS process. Performance analyses in additive-white Gaussian-noise (AWGN) channel environment showed that the bit error rate (BER) of 10 -4 could be achieved at 5 dB and 0.8 dB for SISO and turbo decoders respectively. Implementation result shows that the suggested SISO decoder could achieve throughput in the range 270-810 Mbps with the corresponding power consumption range of 12.24-37.67 mW. In comparison to the state-of-the-art, our design achieved 38% higher throughput and 61% lower power consumption. Similarly, our multi-radix parallel-turbo decoder is hardware prototyped in 28 nm-CMOS Zynq-FPGA board. It delivers a range of data-rates from 160 to 515 Mbps operating at 160 MHz of clock frequency for 8 iterations. Full thesis: pdf Centre for VLSI and Embeded Systems Technology |
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