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A DSL Compiler for Accelerating Image Processing Pipelines on FPGAsAuthor: Nitin chugh Date: 2019-04-03 Report no: IIIT/TH/2019/41 Advisor:Suresh Purini AbstractFuture graphics and imaging applications from self-driving cars, to pervasive sensing, demand orders of magnitude more computation than we currently have. Real graphics and imaging applications appear embarrassingly parallel, but have complex dependencies, and are limited by locality and synchronization. Increasingly, the cost of communication, both within a chip and over a network dominates computation and power consumption. Driven by these trends, writing high-performance image processing code is challenging. To implement these upcoming sophisticated DIP algorithms and to process the large amount of data captured from sources such as satellites or medical instruments, intelligent high speed real-time systems have become imperative. Image processing algorithms implemented in hardware (instead of software) have recently emerged as the most viable solution for improv- ing the performance of image processing systems. The outstanding features which FPGAs offer such as optimization, high computational density, low cost etc, make them an increas- ingly preferred choice of experts in image processing field today. Despite of huge advancements in High-Level Synthesis (HLS) for FPGAs, designers are still required to have detailed knowledge about coding techniques and the targeted architecture to achieve efficient solutions. To address the challenge of productively building efficient,high- performance programs, this thesis describes an automatic approach to accelerate image processing pipelines using FPGAs. An image processing pipeline can be viewed as a graph of interconnected stages that processes images successively. Each stage typically performs a point-wise, stencil, or other more complex operations on image pixels. Recent efforts have led to the development of domain-specific languages (DSL) and optimization frameworks for image processing pipelines. We develop an approach to map image processing pipelines ex- pressed in the PolyMage DSL to efficient parallel FPGA designs. Our approach exploits reuse and available memory bandwidth (or chip resources) maximally. When compared to Dark-room, a state-of-the-art approach to compile high-level DSL to FPGAs, our approach (a) leads to designs that deliver significantly higher throughput, and (b) supports a greater variety of filters. Furthermore, the designs we generate obtain an mprovement even over pre-optimized FPGA implementations provided by vendor libraries for some of the benchmarks Full thesis: pdf Centre for Software Engineering Research Lab |
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