IIIT Hyderabad Publications |
|||||||||
|
Algorithm Based Robust Transistor Sizing for Optimal Power - Delay Designs in CMOS Digital VLSI CircuitsAuthor: Prateek Gupta Date: 2019-07-04 Report no: IIIT/TH/2019/72 Advisor:Zia Abbas AbstractThe need for the more and more number of devices, in turn higher numbers of functions in a single Integrated Circuit (IC) and greater operating speed are the prime reason for the continuous downsizing of CMOS technology. However, such progressive miniaturization of device dimensions in CMOS circuits has also imported an enormous increase in process variability and therefore, performances figures like propagation delays and power dissipation notably the leakage power are severely degraded. Downscaling the technology nodes in CMOS integrated circuits at or below 45nm have fastened the performance of the circuits but at the cost of the power consumption. CMOS Integrated Circuits have expelled the barrier to achieve minimum power consumption undoubtedly, though it is getting quite difficult to achieve desired performances in the circuits in ultra-deep sub-micron regime. This expeditious scaling in IC causes the dominating behaviour of static power over dynamic power. Enormous increase in process variations (due to progressive CMOS technology scaling) along-with the temperature and supply voltage variations are severely degrading the fabrication outcome of digital circuits i.e. circuits are not accomplishing the specification bounds of the required performances. Therefore, process and operating variations aware optimization has become a very essential task in VLSI design. Moreover, many specifications in a circuit have challenging trade-offs, hence demand effective optimization skills. With this vision, this thesis presents various optimization algorithms based robust transistor sizing calculation for various nanoscale CMOS digital circuits. The algorithms used to optimize the fitness function along with constraints set are meta heuristics such as evolutionary based Genetic Algorithm, thermo based Simulated Annealing algorithm, swarm based Artificial Bee Colony and Particle Swarm Optimization algorithm. The objective is to minimize the static i.e. leakage power without degrading the operating frequency (i.e. keeping the propagation delays in bound) and area. Statistical variation aware robust transistor sizing (width/length) is calculated for the various 2 input and 3 input basic logic gates such as AND, OR, NOT, NAND, NOR, XOR, Full-adder etc. and the obtained sizing is used to size the various other complex cells such 32-bit ripple carry adder, carry select adder, carry save adder and multiplier and few ISCAS benchmark circuits. Notably, our methodology targets semi-custom digital design: once the cell library layout are designed, they can be placed wherever needed in a semi-custom design by technology mapping tools. Monte Carlo simulations have been performed for all the logic cells with 50,000 random statistical samples to check the circuit’s yield,which is found to be around 99.8%. The leakage power is reduced up to 88% without giving any penalty to the propagation delay. Also, the author has proposed two novel techniques to minimize the stand by mode leakage power of 1 bit full adder cell and compared their results with the nominal one. The optimization is done for 45nm, 32nm and 22nm metal gate high-k productive technology model. The obtained PVT variations aware transistor sizing (width/length) are used to optimize other full adder based cells. Full thesis: pdf Centre for VLSI and Embeded Systems Technology |
||||||||
Copyright © 2009 - IIIT Hyderabad. All Rights Reserved. |