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Parallel and Pipelined VLSI Implementation of the Modified Radix-2 DIT FFT algorithmAuthor: S HARSHA KEERTHAN Date: 2019-07-20 Report no: IIIT/TH/2019/93 Advisor:Azeemuddin Syed,Shaik Qadeer Qadeer, Mohammed Zafar Ali Khan AbstractThe Discrete Fourier transform (DFT) is one of the most prominent algorithms of signal processing. The algorithm for computing the DFT effectively is known as the Fast Fourier Transform (FFT) algorithm. FFT core is the key component in many of the digital signal processing, Audio, and video signal and telecommunication systems applications and most of the advanced communication systems need an FFT core to process the Orthogonal Frequency Division Multiplexing (OFDM) function. Cooley-Tukey radix-2 FFT algorithm is one of the most popular FFT algorithms which tries to reduce the computational complexity of DFT. In recent times, the use of FFT processors is even more significant and it is rated among the top 10 algorithms with greatest influence on the practice and development of engineering. Since an FFT core is the basic module in all of these applications, the performance and accuracy of the FFT core are of prime importance. Hence, we use the IEEE 754 half precision format to represent the floating point numbers. The increasing demands for speed and performance in some real-time DSP applications make sequential systems inadequate and led to the design of special-purpose parallel FFT processors that include several arithmetic units operating in parallel. In this work, we try to implement the new Modified Radix-2 decimation-in-time (DIT) FFT algorithm with reduced arithmetic complexity which is in the form of Tangent FFT algorithm. As implementation of the Tangent FFT forms is relatively unexplored even though these FFTs give a lot of advantage by reducing the number of computations. This algorithm is implemented using a design which is similar to that of a perfect shuffle architecture as they possess high computation rates by parallel processing and low latencies. Additionally, we proposed a new bit slicing scheme for the IEEE 754 half precision floating representation format to represent the twiddle factors in the proposed architecture to obtain a better implementation of the Modified Radix-2 DIT FFT algorithm. Further, we tried to implement the FFT algorithm using optimal Canonical Signed Digit (CSD) based complex constant multipliers in an attempt to reduce the area occupied by the complex multipliers and increase the precision/SNR of the output. The entire proposed system has been designed using Verilog Hardware description language. All the simulations are performed and verified using Xilinx Vivado tools and synthesis are done on Cadence Encounter RTL compiler with a UMC CMOS 180nm technology library Full thesis: pdf Centre for VLSI and Embeded Systems Technology |
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