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A Novel Impedance Calibration Method for Low Cost Memory ApplicationsAuthor: GOPIKRISHNA SIDDULA Date: 2021-02-22 Report no: IIIT/TH/2021/15 Advisor:Azeemuddin Syed AbstractAs demands for high volume data exchanges increase in many memory applications, significant efforts have been devoted to improving I/O interface performance to achieve high bandwidth. However, the impedance mismatch between I/O driver and a transmitting channel causes signal reflection, interfering with the incoming data in terms of overshoot, undershoot, or ringing. I/O interface requires a minimum variation of output I/O driver impedance over process, temperature, and voltage variations to ensure high-quality signal integrity. The traditional approach of using an external resistor component to generate a constant reference for impedance calibration is not an effective solution considering the constraints due to shrinking package form factor and low-cost limitations of memory applications. This thesis proposes a novel I/O driver impedance calibration architecture and its circuit design using internally generated constant current reference. Also, designed a current mode Bandgap Reference circuit, which generates a constant current across Process and Temperatures variations. A voltage detect circuit is proposed to capture Supply Voltage variations and to compensate the current reference accordingly. To minimize the error in calibration codes, a low offset comparator is designed. IO driver with a combination of MOS device and a series poly resistor is used for better linearity in impedance. This thesis proposes and implements an independent calibration of Pullup and Pulldown IO drivers. The pullup driver calibration codes are not reused for pulldown driver calibration. It reduces the mismatch in impedance of Pullup and Pulldown drivers by eliminating propagation of any quantization error in Pullup calibration codes to Pulldown driver calibration. The proposed calibration scheme and the whole circuit was designed and implemented in 28nm standard CMOS technology using 1.8V supply voltage. In spice simulations of the proposed calibration design/scheme, the impedance variation of both pullup and pulldown driver is approximately +/-7% across process, temperature, and voltage variations. This reduced IO driver impedance variation is achieved using the proposed internally generated constant current source without using any external component resistor. Full thesis: pdf Centre for VLSI and Embeded Systems Technology |
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