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A High PSRR, 11.6ppm/oC, CMOS Current Reference with Integrated Process Auto-Calibration System Process stable current reference architecture ranging 50µA to 50nA to target ultra low power applicationsAuthor: Arpan Jain Date: 2021-04-23 Report no: IIIT/TH/2021/33 Advisor:Zia Abbas AbstractHigh research efforts were put in last century to make systems that could interface people. With the beginning of twenty century, this trend has shifted from systems that interface with people to system that interact with things. Consequently, a huge enthusiasm grew up in researchers, and a new term Internet of things (IoT) is coined. Expectation of these IoT applications have changed from time to time. Current and future emerging IoT applications demand ultra low power, so that these devices could survive with miniaturized batteries. Besides this, lower form factor is desired for biomedical applications to reduce invasive surgeries, as well as to reduce cost of the device. A high supply insensitivity is also desired in these applications. With all these constraints in play, we have put efforts to design current reference and temperature sensor, as they are present in almost every analog and mixed signal system. This thesis focuses on designing a high PSRR ultra low power current references with much reduced form factor and cost. Efforts were first put to develop a high PSRR current reference with process stabilized accuracy. The current reference achieves PSRR of 74dB and line sensitivity of 0.05%. It works for supply voltage variation from 1.4V to 3.6V. The current reference of 50µA and 50nA attain temperature coefficient of 11.6 ppm/oC and 12.2 ppm/oC respectively for the temperature variation of - 55oC to 125oC. The 5MΩ on-chip resistance is required to achieve 50nA current in our architecture. This large resistance increases chip area, hence cost. It has been observed that form factor is compromised in the proposed architecture. Consequently, we have come up with an idea of resistance amplification, that is to get characteristics of large resistance in smaller area. This idea is generic and applicable to many other fields. By integrating resistance amplifier in the proposed current reference architecture, A High PSRR ultra low power reference is achieved with much lesser area. This current reference shows the best figure of merit in terms of area and accuracy till now. However, this reference similar to any other current reference requires post silicon trimming to account for dc shift with process change. Manual trimming is most followed technique to achieve this despite its high cost. Lastly efforts were put to propose an auto-calibration system that replicates the accuracy of manual trimming at much reduced cost. Full thesis: pdf Centre for VLSI and Embeded Systems Technology |
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