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Subsampling CMOS Frontends for Multistandard Reconfigurable RF RadiosAuthor: ajinkya kale Date: 2018-12-10 Report no: IIIT/TH/2018/90 Advisor:Vijaya Sankara Rao P AbstractWith the evolution of wireless systems, more communication standards are being proposed while maintaining backward compatibility, therefore, there is an ever growing need for wideband multistandard receivers similar to software defined radio (SDR) receivers. For many years now, SDR or digitally reconfigurable radio research has been quite challenging with only a few reported practical prototypes with limited success. The basic demand of the SDR has been the need for a giant analog-to-digital converter (ADC) and a powerful enough digital signal processing (DSP) so that it serves as a universal radio platform receiving almost all radio standards and services. These demands are difficult to meet even in modern CMOS technologies leading to the necessity of highly flexible architectures compared to traditional receivers. To achieve this objective, digital intensive receiver architectures with passive structures are proposed. Radio frequency (RF) sampling receivers using time-interleaved (TI), RF sampling and discrete-time mixing also provide additional flexibility by employing discrete-time signal processing in analog domain. Owing to the oversampling ratio of up to 8 times in these receivers, high-performance complex frequency synthesizers are needed with stringent phase noise requirement. Moreover, the clocking schemes employed in TI RF sampling architectures result in additional timing jitter and mismatch offsets. These challenges are alleviated in a class of sampling receivers, called subsampling receivers, where the employed bandpass sampling principle results in less than the Nyquist sampling frequency. This leads to the less-complex and less power hungry frequency synthesizers. In this thesis, an intermediate solution to SDR receiver implementation called “Mini-SDR” architecture is proposed by exploiting the bandpass sampling concept. Based on the proposed Mini-SDR architecture, three CMOS radio frontends are proposed for standalone electronic attack (EA) transceiver system, dynamically reconfigurable multistandard subsampling (DRMS) radio receiver and a dual-band subsampling receiver for IEEE WLAN 802.11ac standard. The first architecture is a single chip integrated transceiver for a standalone EA system based on digital radio frequency memory (DRFM) repeater without the need for a separate instantaneous frequency measurement (IFM) receiver. The proposed transceiver architecture employs sub-Nyquist discrete-time frontend to estimate the carrier frequency and bandwidth of the incoming pulse radar signals. The system is verified for linear frequency modulated, constant carrier frequency and phase coded pulse radar signals. These signals are classified on the basis of Wigner-Ville distribution. The performance of the proposed system is validated from 1 GHz to 20 GHz with instantaneous bandwidth of 300 MHz, dynamic range from −60 dBm to −20 dBm and system gain from 30 dB to 60 dB. The minimum delay achieved between reception and retransmission is 13 pulse repetition intervals (PRIs). To the best of author’s knowledge, this work reports the first sub-Nyquist bandpass sampling based single chip architectural solution for a standalone EA system where RF frontend and digital controller are integrated into the system. The second architecture is the DRMS radio receiver. The proposed receiver has a unique capability to detect the carrier frequency of the incoming signal, estimate it’s bandwidth and standard. The RF frontend is modelled in Verilog-AMS behavioural model and the digital signal processing is implemented in Simulink-Matlab. Also, the system level optimizations of the overall receiver performance are presented with the effect of receiver impairments. The complete receiver architecture has been verified to detect and process three different bands belonging to three different standards (GSM, UMTS and WLAN) with the carrier frequency ranging from 0.9 GHz to 2.5 GHz with a maximum signal bandwidth of 22 MHz and the input dynamic range from −109 dBm to −20 dBm. The last implementation is a first dual-band subsampling receiver with subsampling frequency optimization to meet ultimate receiver error vector magnitude (EVM) of −40 dB over wide input power range of 19 dB. Systematic system level optimization of the receiver chain with major impairments such as sampling frequency, synthesizer phase noise, IQ mismatch and unit capacitor in the SC filter is also proposed. Sampling frequency optimization proposed in this work has multi-fold advantages: a) the noise folding effect is reduced leading to smaller noise figures. b) less-complex and less-power hungry clocking scheme. c) quadrature phase readily available between consecutive samples is utilized to separate samples into in-phase (I) and quadrature-phase (Q) paths. d) the ultimate EVM performance of the receiver is significantly better than the subsampling receivers, where the sampling frequency is not optimized. The dual-band subsampling receiver has 26 dB to 40 dB continuously tunable gain and 4.7 GHz to 5.7 GHz continuously tunable frequency band. The subsampling down-conversion mixer is employed to down-convert both 2.4 GHz and 5 GHz WLAN bands to a low intermediate frequency from 445 MHz to 538 MHz with clock frequency in the range from 1.78 GHz to 2.15 GHz, thanks to subsampling. Additionally, a switched capacitor decimation filter is utilized to provide dual functionality of 2 down-conversion to baseband and band selection. The proposed IEEE 802.11ac WLAN dual-band subsampling receiver test-chip is implemented in 1.2 V 65-nm CMOS technology to prove the concepts proposed, including major system level, circuit level and layout level optimizations. The test-chip occupies a total active area of 0.72 mm2 with a total power dissipation of 61 mW. To the best of author’s knowledge, this is the first subsampling based receiver to report high-frequency band 4.5 GHz to 5.7 GHz with channel bandwidths up to 40 MHz. Also, the measured ultimate EVM floor of −40 dB over a wide input power range of 19 dB is demonstrated which is far superior to the published sub-sampling receivers. In this thesis, CMOS frontends were modelled, designed, simulated fabricated and measured to prove the proposed concepts for multistandard subsampling radios. Full thesis: pdf Centre for VLSI and Embeded Systems Technology |
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