Design of CMOS Proteretic Device and its Applications

Abstract

The semiconductor industry is driven by the need to design smaller, faster and low power con- suming circuits. A comparator is an integral part of any electronic system and by default the comparators exhibit hysteresis phenomenon. A Schmitt trigger is the most commonly used comparator in circuit design. Rigorous efforts have been made to speed up the circuit perfor- mance by various techniques at the system, circuit and transistor level and they have demon- strated incremental improvement. However, all these efforts are focused on reducing the switch- ing time between the logic levels and shortening the width of hysteretic loop while maintaining noise immunity. This thesis presents a new paradigm shift from the conventional techniques of circuit speed up wherein the hysteretic device itself is replaced with a proteretic one and efforts to improve the circuit speed have been demonstrated successfully. Hysteresis has an inherent switching delay, whereas, proteresis or inverse hysteresis demonstrates an early response to the switching action of the circuit. Proteresis is a known phenomenon across various domains like pharmacokinetics (PK) and pharmacodynamics (PD) drugs, ferro-electric materials and optical bi-stable devices, but their impact and study in area of Integrated circuits has been very limited. This is because proteresis is induced by feed forwarding the input to couple of hysteretic devices (Schmitt trigger) and this leads to output of circuit being stable for a small input ranges and prevalent instability over the remaining input range. However, this thesis proposes a novel mechanism of stabilizing the proteretic output over a wide input voltage range and hence leverages the benefit of early switching characteristics for improving the circuit speed by a factor of 25%. A detailed mathematical model for proteretic circuit design over various input ranges is presented and the trade-off in terms of area and power is also discussed with the ramp generator as a design example. Hysteretic and proteretic devices are bi-stable and their interstate switching depends on triggering voltages. Conventionally, devices can be classified to work as either hysteretic or proteretic. This thesis proposes the first attempt to describe a circuit that switches between two opposite characteristics of hysteresis and proteresis to present a new circuit called Prohys switch. The output of prohys switch demonstrates a limited amount of randomness in its first cycle of operation and this factor is a strong reason to employ a prohys switch for designing a Physical unclonable Function (PUF). In recent times PUF’s has gained immense popularity for securing the IC’s by providing unique identification code to each chip. The key design parameters of a PUF are uniqueness and reliability and designing a highly efficient PUF with optimal values of uniqueness and reliability is quite a challenge. Reliability depends on the chip’s ability to resist changes to supply voltage and temperature variations, whereas, uniqueness depends on process variations during chip fabrication. Multiple PUF designs that employ reliability enhancement circuits and security algorithms achieve these design characteristics. Nonetheless, these techniques are design overheads. Finally, this thesis presents a novel PUF based on the proHys switch called the prohys PUF. The proposed prohys PUF befittingly satisfies both uniqueness and reliability criteria, without any additional circuitry or security algorithms.