A PVT-aware Surrogate Modeling Framework for Digital, Analog, and Mixed-Signal VLSI Circuits

Abstract

The invention of Complementary Metal–Oxide–Semiconductor (CMOS) transistors marked a revolutionary shift in the field of electronics, ushering in the era of semiconductor devices within the Integrated Circuit (IC) industry. Since then, CMOS technology has dominated the realm of microelectronics. The key to advancing ICs lies in transistor scaling, which boosts transistor density, switching speed, and operational frequency, enabling the creation of higher-performing electronic circuits. However, the aggressive down-scaling of CMOS technology has posed challenges for device engineers while opening up new opportunities. As transistor dimensions decrease, the complexity of the semiconductor process increases. As we approach atomic scales, simple scaling reaches its limits. Despite their minute size, devices can encounter various performance issues, including increased leakage, reduced gain, and increased sensitivity to manufacturing process variations. The substantial rise in process variations significantly impacts circuit operation, resulting in variable performance even in transistors of identical size. This, in turn, affects the propagation delay of the circuit, which behaves as a stochastic random variable, making timing-closure techniques more complex and exerting a substantial influence on chip yield. FinFETs, which have superseded CMOS in the nanoscale IC designs, also face performance deviations due to process variations despite demonstrating good resistance to Short Channel Effects (SCE). Surging process variations in the nanometer regime significantly contribute to the degradation of parametric yield. Under such scenarios, the Process, Voltage, and Temperature (PVT) aware performance estimation of VLSI circuits through traditional Electronic Computer Aided Design (E-CAD) tools is a complex endeavor. These tools often exhibit intricacies, heavily relying on specific circuit architectures and licensing agreements, while demanding significant simulation times proportional to the design complexity. Moreover, conventional tools tend to adhere rigidly to standardized processes and workflows, potentially limiting their efficacy and stifling innovation by confining designers to predetermined methodologies. Furthermore, the traditional approaches employed for such tasks frequently involve manual intervention, introducing time-sensitive and resource-intensive procedures that can contribute to delays in the time-to-market. Additionally, upon receiving simulation results, designers may face challenges in comprehending the underlying functionalities, including identifying the root causes of issues and implementing necessary fixes. This can result in additional time consumption and impede the overall design iteration process. The objective of this research is to develop a rapid and efficient surrogate modeling framework to precisely predict PVT-aware circuit performance within Very Large Scale Integration (VLSI) circuits,with a focus on overcoming the limitations of conventional modeling approaches. The framework is designed to be versatile, platform-independent, and capable of modeling a wide range of digital, analog, mixed-signal, and RF circuit applications. To accomplish these objectives, we integrate Artificial Intelligence (AI) and Machine Learning (ML) based surrogate models into the framework to monitor circuit performance under the influence of PVT variations. The framework encompasses several stages, including PVT-aware simulation data generation, the development of a bank of AI/ML models employing supervised learning representing each circuit under consideration, and a high-level intelligent entity responsible for identifying the most effective model. To demonstrate the methodology, our framework incorporates 22 statistically aware standard digital logic circuits and various application-specific datasets for analog circuits, considering the impacts of design, process, and environmental variations across multiple technology nodes. Digital circuit modeling spans high-performance CMOS technology nodes, namely 45nm, 32nm, 22nm, and 16nm, and FinFET technology nodes, such as 16nm, 10nm, and 7nm. Analog, mixed-signal, and RF circuit modeling encompasses designs ranging from 180nm to 65nm and 28nm technology nodes. Moreover, the framework utilizes an automated methodology for estimating the performances of complex digital circuits, grounded in statistical variations within standard cells and facilitated by the most accurate AI/ML model. This methodology is versatile and applicable to a broad spectrum of digital circuits, eliminating the need for generating labor-intensive simulations tailored to individual circuits. It offers a streamlined solution that can be readily adapted across various circuit designs, saving considerable time and resources typically invested in customized simulation configurations for each circuit type. Additionally, we expand the PVT-aware surrogate modeling approach to optimize transistor sizing for improved yield, achieving a reduction of up to 64.6% in Power-Delay Product (PDP) of ISCAS-74X and ISCAS-85 benchmark circuits. Furthermore, the research delves into the computational hurdles entailed in generating a significant volume of simulation samples for each targeted technology node, while considering diverse sources of variation. Consequently, it introduces the concept of transfer learning to circuit modeling, entailing a comprehensive exploration of relationships within CMOS/FinFET technologies across various technology nodes. The objective is to furnish precise predictions of PVT-aware circuit performance at advanced process nodes, thereby diminishing the considerable data requirements typically associated with such modeling endeavors. This is accomplished by capitalizing on knowledge accumulated during circuit modeling from one technology node to another. Additionally, the research concentrates on extrapolating PVT-aware performance onto forthcoming/future nodes by leveraging insights obtained from established nodes. It is noteworthy that this framework adopts a black-box approach, facilitating the incorporation of any number of PVT variations in any desired technology node with minimal computational complexity. This adaptive methodology not only enhances efficiency but also facilitates the flexibility to accommodate diverse circuit designs and technological advancements. In addition, this research integrates rapid sensitivity analysis methods alongside a systematic approach to pinpointing predominant parameters, leveraging extensive statistical datasets encompassing both digital and analog elements. The framework adeptly constructs models for analog and mixed-signal circuits with precision using the dominant parameters. These developed analog models present practical solutions for implementing self-adapting microelectronic circuits via appropriate digital control logic, thereby alleviating performance discrepancies stemming from PVT variations. These models not only enhance the adaptability and efficiency of circuit designs but also propel the microelectronics domain forward by facilitating dynamic responses to fluctuating operational environments, ultimately fostering innovation and advancement.